1. Field
This disclosure relates generally to analog-to-digital conversion circuits, and more specifically, to continuous time sigma/delta analog-to-digital conversion circuits.
2. Related Art
Sigma/delta analog-to-digital converters (ADCs) are incorporated in various signal conversion applications. Some sigma/delta analog-to-digital converters use discrete time techniques to inject a feedback analog signal into the feedback loop filter and others use a continuous time technique. Discrete feedback in a sigma/delta analog-to-digital converter is typically implemented by using switch capacitor techniques for the integrators and a feedback digital-to-analog converter. During portions of the sample clock, charge transfer is taking place on and off the capacitors inside the integrator and inside the feedback digital-to-analog converter sub-blocks. Clock jitter on the pulse width of the sample clock has the effect of modulating the pulse width of the sample clock in a random manner. Discrete time feedback techniques only require that the charge be transferred on or off the capacitor during that portion of the clock, thus eliminating the effect of jitter on the sample clock pulse width. Continuous time feedback techniques generally use current or voltage sources which are gated on or off directly by the sample clock. As sample clock pulse width jitter randomly modulates the pulse width of the sample clock, the feedback coefficients are also being effectively randomly modulated as well because the time during which current or voltage is provided to the feedback filter (and thus integrated) varies from sample to sample. Sample clock pulse width jitter therefore has a major effect on the signal-to-noise ratio of the sampled signal.
Using discrete time feedback techniques generally requires higher current drain in a sigma/delta analog-to-digital converter than using continuous time feedback techniques. The additional current drain for discrete feedback techniques is due, for example, to the fact that such circuits perform at the sampling clock rate and must support large instantaneous currents as the capacitor charge transfer takes place, without slew-rate limiting the integrator output signal. In contrast, continuous time feedback techniques are only required to respond across the band of interest. Overcoming problems associated with sample clock pulse width jitter is a challenge in realizing continuous time feedback techniques in a sigma/delta analog-to-digital converter. Sample clock pulse width jitter randomly varies the timing of the clock edges and is usually specified in pico-seconds (ps). Clock pulse width jitter affects all analog-to-digital converters by degrading the signal-to-noise ratio (SNR) of the sampled signal and thereby effectively reducing a converter's dynamic range and increasing the noise level.